1. Field of the Invention
The present invention relates to the field of generation of timing pulses having precise delays and more particularly to synchronous delay lines as used in metal-oxide semiconductor (MOS) integrated circuits.
2. Related Application
This application is related to copending application, Ser. No. 07/434408, filed 11/13/89, and entitled "Synchronous Delay Line with Quadrature Clock Phases".
3. Prior Art
In an integrated circuit, having a memory, processor, and/or other circuitry, it is necessary to have clocking or timing signals for various uses, such as latching of address signals, decoding the address signals and etc. One technique of generating "on-chip" timing signals is by the use of a synchronous delay line. Prior art techniques of utilizing a synchronous delay line are described in U.S. Pat. No. 4,496,861 entitled "Integrated Circuit Synchronous Delay Line" and in an article entitled "A Novel Precision MOS Synchronous Delay Line", IEEE Journal of Solid State Circuits, Volume SC-20, pp. 1265-1271, December 1985. The synchronous delay line is used to generate timing pulses designed to have precise delays from the start of a clock period. This particular synchronous delay line receives a clock reference signal and provides a series of taps, wherein each tap provides a timing pulse that has a precise delay from the commencement of a clock cycle which is initiated by the reference clock.
Although the synchronous delay line described in the above-mentioned prior art references provides for on-clip timing signals having very high timing accuracy and which is also insensitive to variations due to processing, supply voltage and temperature, it has a disadvantage in that a reset scheme is needed.
Typically the synchronous delay lines require a reset during power-up, in order to assure that the synchronous delay line enters its fundamental mode of operation. In the prior art synchronous delay lines, such as that described in U.S. Pat. No. 4,496,861, the delay line requires an externally generated reset signal to provide the reset function during power-up. However, integrated circuit devices utilizing external resets typically require a reset pin dedicated to receiving such an external reset signal. Furthermore, since the SDL requires many clocks (typically several hundred clocks) to achieve steady-state operation after reset, the operation of the integrated circuit device utilizing the SDL must be inhibited after reset during the time the SDL is not in the steady-state.
As will be seen, the present invention provides for an internal reset scheme, so that external reset inputs are not required and, therefore a reset pin need not be dedicated for receiving the external reset signal. Likewise, the internal reset scheme allows the SDL to achieve steady-state operation well before system reset is complete, so that the SDL is already in its steady state when reset is complete, and the operation of the integrated circuit device utilizing the SDL need not be inhibited.